DFT 2011 - Call for Papers

CALL FOR PAPERS

Scope -- Submissions -- Key Dates -- Additional Information -- Committees

Scope

DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation are of interest.

The topics include (but are not limited to) the following ones:

Yield Analysis and Modeling
Defect/Fault analysis and models; statistical yield modeling; critical area and metrics.
Testing Techniques
Built-in self-test; delay fault modeling and diagnosis; testing for analog and mixed circuits; signal and clock integrity.
Error Detection, Correction, and Recovery
Self-testing and self-checking solutions; error-control coding; fault masking and avoidance; recovery schemes, space/time redundancy; hw/sw techniques.
Design For Testability in IC Design
FPGA, SoC, NoC, ASIC, microprocessors.
Dependability Analysis and Validation
Fault injection techniques and environments; dependability characterization.
Defect and Fault Tolerance
Reliable circuit & system synthesis; radiation hardened/tolerant processes & design; design space exploration for dependable systems, transient/soft faults and errors.
Repair, Restructuring and Reconfiguration
Repairable logic, reconfiguration, repair; reconfigurable circuit design; DFT for on-line operation; self-healing.
Totally Fail-Safe Design for Critical Applications
Methodologies and case study applications to automotive, railway, avionics, industrial control, biomedicine, space and smart power networks.
Emerging Technologies
Techniques for CNTs, QCA, DNA, RTDs, SETs, molecular devices and self-assembly.

Submissions

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Prospective authors should prepare an extended summary or the full paper (up to 7 pages in the IEEE 6X9 single column format), to be submitted as PDF file. Submission should be done electronically. Detailed information about the submission process will be made available on the symposium web page:

http://www.dfts.org

We are also interested in panel sessions that involve industrial experiences: please send an email to the Program co-Chairs with a brief description (1 page maximum) of the panel discussion
you would like to propose.

Paper Publication and Author Registration: Only original, unpublished work will be accepted, for regular or poster presentation at the symposium. Proceedings will be published by the IEEE Computer Society and will appear in the Digital Library.

Every accepted paper MUST have at least one full paid registration by the time the camera-ready paper is submitted for inclusion in the proceedings. The author is also expected to attend the Symposium and present the paper.

Best Student Paper Award: All papers with a student as both primary author and presenter will be taken into consideration for the 2011 Best Student Paper Award, sponsored by Intel.

Journal Special Issue: There is a possibility for inviting the authors of selected papers presented
at DFT 2011 to submit an extended version of their work in a special issue of an archival journal.

Key Dates

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Submission deadline: May 7, 2011
Notification of acceptance: June 29, 2011

Additional Information

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General Information

Glenn Chapman
General Co-Chair
Simon Fraser University, Canada
E-mail: glennc@ensc.sfu.ca

Fabio Salice
General Co-Chair
Politecnico di Milano, Italy
E-mail: fabio.salice@polimi.it

Submission Information

Prashant D. Joshi
Program Co-Chair
Intel, U.S.A
E-mail: prashant.d.joshi@intel.com

Massimo Violante
Program Co-Chair
Politecnico di Torino, Italy
E-mail: massimo.violante@polito.it

Committees

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General co-Chairs
Glenn Chapman
Simon Fraser University, Canada
E-mail: glennc@ensc.sfu.ca

Fabio Salice
Politecnico di Milano, Italy
E-mail: fabio.salice@polimi.it

Program co-Chairs
Prashant D. Joshi
Intel, U.S.A
E-mail: prashant.d.joshi@intel.com

Massimo Violante
Politecnico di Torino, Italy
E-mail: massimo.violante@polito.it

Publicity Chair
Antonio Miele
Politecnico di Milano, Italy
E-mail: miele@elet.polimi.it

Program Committee
M. A. Aguirre Echanove, University of Seville
P. Ampadu, University of Rochester
C. Bolchini, Politecnico di Milano
S. Chakravarty, LSI Logic
Y. Choi, Hongik University
A. Daniel, Intel
L. Dilillo, LIRMM
B. Eklow, CISCO
M. Favalli, University of Ferrara
M. Fukushi, Tohoku University
D. Gizopoulos, University of Piraeus
S. Hamdioui, Delft University of Technology
J. Han, University of Alberta
C. Huang, Nat’l Tsing Hua U.
A. Jas, Intel
N. Jha, Princeton
W. Jone, University of Cincinnati
R. Karri, Polytechnic Institute of NYU
Y. Kim, Northeastern University
I. Koren, UMASS Amherst
R. Leveugle, TIMA labs
F. Lombardi, Northeastern University
C. Metra, University of Bologna
F. Miller, EADS
N. Nicolici, McMaster University
M. Ottavi, University of Rome “Tor Vergata”
N. Park, Oklahoma State University
A. Paschalis, University of Athens
Z. Peng, Linkoping University
W. Pleskacz, Warsaw U.T.
S. Pontarelli, University of Rome “Tor Vergata”
M. Rebaudengo, Politecnico di Torino
S. Reddy, University of Iowa
A. Salsano, University of Rome “Tor Vergata”
D. Sciuto, Politecnico di Milano
M. Tehranipoor, University of ConnecticutJ. Teixeira, INESC-ID Lisboa
C. Thibeault, Ecole de Tech.
N. Touba, University of Texas at Austin
S. Tragoudas, Southern Illinois Univ. Carbondale
R. Velazco, TIMA labs
L. Wang, University of Connecticut
X. Wen, Kyushu Institute of Technology

For more information, visit us on the web at: http://www.dfts.org

The IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2011) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society, Technical Committee on Fault-Tolerant Computing, and Test Technology Technical Council (TTTC).